Intel OR840 BIOS Post Codes:
|
POST Code (port 0x80)
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POST Code (port 0x81)
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Description
|
| 01 | Transition to protected mode complete | |
| 30 | Seek relevant processor patch | |
| 31 | Apply processor patch | |
| 32 | Setup ICH GPIO base, SIO PME base, miscellaneous ICH settings | |
| 33 | Setup ICH and SIO GPIO attributes and values | |
| 3A | Set ICH GPIO attributes and values | |
| 3B | Set SIO GPIO attributes for GPIO10-17 | |
| 3C | Set SIO GPIO attributes for GPIO20-27 | |
| 3D | Set SIO GPIO attributes for GPIO30-37 | |
| 3E | Set SIO GPIO attributes for GPIO40-43 | |
| 3F | Set SIO GPIO attributes for GPIO50-57 | |
| 40 | Set SIO GPIO attributes for GPIO60-61 | |
| 41 | Set initial values for SIO GPIOs | |
| 34 | SMBUS initialization | |
| 35 | Initialize L1 cache for use as memory during memory initialization | |
| 02 | Start Minimum memory establishment | |
| 00 | Memory not supported (Not RDRAM) | |
| 01 | Memory not supported (SPD contains invalid width - not 16 or 18) | |
| 02 | No memory devices were found on one or both channels | |
| 03 | More than 32 devices on the channel | |
| 04 | Memory failure (number of devices detected does not match SPD data) | |
| 05 | Memory not supported (FRAS data in SPD is invalid) | |
| 0A | Memory not supported (Populated memory requires too many time domains) | |
| 0B | Memory not supported (No valid channel frequency) | |
| 0C | Memory failure (levelization failure 0 ran out of time domains) | |
| 0D | Memory not supported (unsupported memory technology) | |
| 0E | Memory failure (Continuity module missing or chipset failure) | |
| 0F | Memory not supported (could no find valid refresh rate | |
| 10 | Memory not supported (invalid refresh information in SPD | |
| 11 | Memory not supported (TCDC invalid) | |
| 12 | Memory not supported (does not support enough time domains) | |
| 13 | Memory not supported (TRDC invalid) | |
| 14 | Memory not supported (invalid SPD TCLS or TCAS) | |
| 15 | Memory not supported (SPD mismatch between channel A and B) | |
| 17 | Memory not supported (SPD mismatch between channel A and B) | |
| 18 | Memory not supported (SPD mismatch between channel A and B) | |
| 19 | Memory not supported (SPD mismatch between channel A and B) | |
| 1A | Memory not supported (SPD mismatch between channel A and B) | |
| 1B | Memory not supported (SPD mismatch between channel A and B) | |
| 1C | Memory not supported (SPD mismatch between channel A and B) | |
| 1F | Memory not supported (SPD mismatch between channel A and B) | |
| 20 | Memory not supported (invalid number of devices on RIMM) | |
| 22 | Memory not supported (SPD mismatch between channel A and B) | |
| 24 | Memory failure (Detected bad chipset configuration) | |
| 25 | Memory not supported (RIMMs must support ECC) | |
| 28 | Memory not supported (unsupported memory technology) | |
| 29 | Memory not supported (unsupported memory technology) | |
| 2A | Memory not supported (could not find valid CAS latency) | |
| 2C | Memory not supported (can not mix registered and non-registered memory | |
| 2D | Memory not supported (could not find valid CAS latency) | |
| 2E | Memory failure (levelization phase 1) | |
| 2F | Memory failure (levelization phase 2) | |
| 38 | Start memory discovery | |
| 40 | STEP: Setup for memory discovery | |
| 41 | STEP: SIO reset | |
| 42 | STEP: Serial enumeration | |
| 44 | RDRAM STEP: Detect RIMM presence using SPD | |
| 45 | RDRAM STEP: DRCG bypass mode - SIO RESET/SET RESET/CLEAR RESET | |
| 46 | RDRAM STEP: Determine RAMBUS frequency and set DRCG | |
| 47 | RDRAM STEP: MCH RAC initialization | |
| 48 | RDRAM STEP: Page Policy and power management (initialization mode) | |
| 4A | RDRAM STEP: Test 77 | |
| 4B | RDRAM STEP: Serial enumeration | |
| 4C | RDRAM STEP: Group enumeration | |
| 4D | RDRAM STEP: Program timing parameters | |
| 4E | RDRAM STEP: Power down exit | |
| 4F | RDRAM STEP: Fast clock initialization | |
| 50 | RDRAM STEP: RDRAM core initialization | |
| 51 | RDRAM STEP: Levelization | |
| 52 | RDRAM STEP: Program power down configuration options | |
| 53 | RDRAM STEP: Begin normal operations - Page Policy and power management and IC bit | |
| 54 | RDRAM STEP: memory initialization complete - reenter MIT | |
| 55 | RDRAM STEP: Program power down configuration options | |
| 56 | RDRAM STEP: Begin normal ops - Page Policy and power management and set IC bit | |
| 57 | RDRAM STEP: Memory initialization complete - reenter MIT | |
| 03 | Found quick start VM0 FMM object | |
| 30 | Seek relevant processor patch | |
| 31 | Apply processor patch | |
| 32 | Setup ICH GPIO base, SIO PME base, miscellaneous ICH settings | |
| 33 | Setup ICH GPIO attributes and values | |
| 3A | Set ICH GPIO attributes and values | |
| 3B | Set SIO GPIO attributes for GPIO10-17 | |
| 3C | Set SIO GPIO attributes for GPIO20-27 | |
| 3D | Set SIO GPIO attributes for GPIO30-37 | |
| 3E | Set SIO GPIO attributes for GPIO40-43 | |
| 3F | Set SIO GPIO attributes for GPIO50-57 | |
| 40 | Set SIO GPIO attributes for GPIO60-61 | |
| 41 | Set initial values for SIO GPIOs | |
| 34 | SMBUS initialization | |
| 35 | Initialize L1 cache for use as memory during memory initialization | |
| 04 | Memory established | |
| 60 | Prepare for ECC scrubbing | |
| 61 | ECC scrubbing | |
| 62 | Restore context after ECC scrubbing | |
| 63 | Exit SMBUS | |
| 64 | ICH settings | |
| 66 | PIC | |
| 68 | SIO - Parallel port | |
| 69 | SIO - Serial port #1 | |
| 6A | SIO - Serial port #2 / DMA | |
| 6B | SIO - Game port | |
| 6C | SIO - MIDI | |
| 6D | SIO - Exit configuration | |
| 6E | Local APIC, FWH decode, runtime enable | |
| 05 | Enable paging | |
| 06 | Unpack VM2 | |
| 07 | Transition to VM2 | |
| 30 | Interposer entry | |
| 01 | Interposer - Phase 0 - CMOS initialization | |
| 02 | Interposer - Phase 0 - IVT initialization | |
| 03 | Interposer - Phase 0 - Initialize compatibility table | |
| 04 | Interposer - Phase 0 - Runtime mouse fixes | |
| 11 | Interposer - Phase 1 - Reserved | |
| 12 | Interposer - Phase 1 - SCSI device numbering | |
| 21 | Interposer - Phase 2 - E820 data transfer | |
| 22 | Interposer - Phase 2 - Data repackaging | |
| 23 | Interposer - Phase 2 - Int 13h post | |
| 24 | Interposer - Phase 2 - Reserved | |
| 3A | 31 | Interposer - VM3 entry - Reserved |
| 32 | Interposer - VM3 entry - Entering Int 19h | |
| 3F | DCC | |
| 40 | XY | Scan for devices on PCI BUS where XY : X = Device(bits 7 - 3), Y = Bus(bits 2 - 0) |
| 41 | Route PCI IRQs to devices | |
| 42 | Allocate memory resources to PCI devices | |
| 43 | Allocate IO resources to PCI devices | |
| 44 | Detect and shadow PCI Option ROM - Add in card | |
| 45 | Detect and shadow PCI Option ROM - Embedded | |
| 4F | PCI Enumeration complete | |
| 50 | SEL_FLASH_GetMaxRecSize had a severe parity error reading flash | |
| 70 | Enumerate primary IDE channel | |
| 02 | Test for empty primary IDE channel | |
| 03 | Primary IDE channel discovery complete | |
| 04 | Primary IDE channel - check for ATAPI signature - master | |
| 05 | Primary IDE channel - master found - look for slave | |
| 16 | Primary IDE channel - ATAPI slave found | |
| 26 | Primary IDE channel - slave found | |
| 36 | Primary IDE channel - slave found | |
| 71 | Enumerate secondary IDE channel | |
| 82 | Test for empty secondary IDE channel | |
| 83 | Secondary IDE channel discovery complete | |
| 84 | Secondary IDE channel - check for ATAPI signature - master | |
| 85 | Secondary IDE channel - master found - look for slave | |
| 96 | Secondary IDE channel - ATAPI slave found | |
| A6 | Secondary IDE channel - slave found | |
| C6 | Secondary IDE channel - slave found | |
| 72 | Program IDE chipset settings | |
| 73 | Program IDE devices | |
| 74 | Setup IDE runtime data | |
| 75 | Hard disk spin-up delay and Drive diagnostics | |
| 90 | SIO initialization - Flex card detection | |
| 91 | SIO initialization - serial | |
| 92 | SIO initialization - parallel | |
| 93 | SIO initialization - keyboard controller | |
| 94 | SIO initialization - FDC | |
| 95 | Initialization - audio | |
| A0 | SMI handler - ACPI mode enable | |
| A1 | SMI handler - ACPI mode disable | |
| A2 | ACPI_LOAD_FACS | |
| A3 | ACPI_LOAD_FACD | |
| A4 | ACPI_LOAD_RSDT | |
| A5 | ACPI_LOAD_DSDT | |
| A6 | ACPI_LOAD_SSDT | |
| A7 | ACPI_LOAD_APIC | |
| A8 | TBD | |
| A9 | TBD | |
| AA | TBD | |
| AB | TBD | |
| AC | ACPI_NO_CATALOG | |
| AD | TBD | |
| AE | ACPI_E820 | |
| AF | ACPI_FIXUPS | |
| B8 | 00 | AGP Pro Detected, prevent system from booting |
| B9 | 00 | FMM initialization failed - Flash corruption - BIOS crisis recovery required |
| DE | AD | Double BIT ECC error detected (forced hang) - This POST code may be only temporary |
| F0 | Enter BIOS recovery mode | |
| F2 | BIOS recovery - initialize flash | |
| F4 | BIOS recovery - enumerate PCI buses | |
| F6 | BIOS recovery - initialize floppy controller | |
| F8 | BIOS recovery - Extract BIOS update file from floppy | |
| F9 | BIOS recovery - Validate BIOS update contents | |
| FA | BIOS recovery - Erase FWH blocks | |
| FB | BIOS recovery - Enable FWH security | |
| FC | BIOS recovery - Write buffer to FWH | |
| FE | BIOS recovery - Operation successful | |
| FF | F1 | BIOS recovery - Flash initialization failure |
| F2 | BIOS recovery - Flash update operation failed | |
| F3 | BIOS recovery - Read file from floppy operation failed | |
| F4 | BIOS recovery - Flash erase operation failed | |
| F5 | BIOS recovery - Flash write operation failed | |
| F6 | BIOS recovery - File verify operation (checksum) failed | |
| F7 | BIOS recovery/flash update - processor patch installation failed | |
| F8 | BIOS recovery - File verify operation (invalid BIOS ) failed | |
| F9 | BIOS recovery - File verify operation (mismatched platform BIOS) failed | |
| FA | BIOS recovery - Boot block incompatible with BIOS | |
| FB | BIOS recovery - Flash verify after write failed |